1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device having an electrostatic prevention circuit and a method for fabricating the same by using a diffraction exposure process.
2. Discussion of the Related Art
Demands for various display devices have increased with the development of information society. Accordingly, many efforts have been made to research and develop various types of flat display devices, such as liquid crystal display (LCD), plasma display panel (PDP), electroluminescent display (ELD), and vacuum fluorescent display (VFD). Some types of flat display devices have already been used as displays in various applications.
Among the types of flat display devices, liquid crystal display (LCD) devices have been most widely used due to advantageous characteristics of thin profile, lightness in weight, and low power consumption, whereby the LCD devices provide a substitute for a Cathode Ray Tube (CRT). In addition to mobile type LCD devices such as a display for a notebook computer, LCD devices have been developed for computer monitors and televisions to receive and display broadcasting signals.
Despite various technical developments in the LCD technology having applications in different fields, research in enhancing the picture quality of the LCD device has been, in some respects, lacking as compared to other features and advantages of the LCD device. In order to use LCD devices in various fields as a general display, the key to developing LCD devices depends on whether LCD devices can realize a high quality picture, such as high resolution and high luminance with a large-sized screen, while still maintaining lightness in weight, thin profile, and low power consumption.
In general, the LCD device includes an LCD panel for displaying an image and a driver for supplying a driving signal to the LCD panel. In addition, the LCD panel includes first and second substrates bonded to each other. A liquid crystal layer is positioned in a cell gap between the first and second substrates. The first substrate (referred to as a TFT array substrate) includes a plurality of gate lines arranged along a first direction at fixed intervals, a plurality of data lines arranged along a second direction perpendicular to the first direction at fixed intervals, a plurality of pixel electrodes arranged in a matrix-type configuration within pixel regions defined by the gate and data lines, and a plurality of thin film transistors transmit signals from the data lines to the pixel electrodes in accordance with signals supplied to the gate lines. The second substrate (referred to as a color filter array substrate) includes a black matrix layer that prevents a light leakage from portions of the first substrate except at the pixel regions, an R/G/B color filter layer for displaying various colors, and a common electrode for producing an image. Alignment layers are respectively formed on opposing surfaces of the first and second substrates, wherein the alignment layers are rubbed to align the liquid crystal layer. Then, the first and second substrates are bonded together by a sealant, and liquid crystal is injected between the first and second substrates.
In the fabrication process of the aforementioned LCD device, the LCD device may be damaged due to static electricity. That is, since the static electricity applies high energy to the LCD device in a short time (in several tens nanoseconds), the LCD device may be damaged. Static electricity has different characteristics depending on the generation source of the electricity. There are different static electricity generations including HBM (human body model), MM (machine model), and CDM (charged device model). Based on these models, electrostatic prevention circuits have been actively developed.
The HBM is modeled on the case of the static electricity induced by the human body. The MM is modeled on the static electricity generated when electric charges of a transport machine or a box are discharged to the LCD panel. The CDM is modeled on the case of static electricity being charged to the LCD panel by electricity generated by friction during the transport or when the LCD panel is touched to a socket or a conductor during the fabrication. Specific portions of the substrate of the LCD panel, used as paths of electricity discharge, are damaged due to such static electricity discharges.
Accordingly, it is prudent to provide an electrostatic prevention circuit inside the LCD device such that internal components of the LCD device are protected from the static electricity. That is, the electrostatic prevention circuit protects the LCD device from static electricity. Also, while driving the LCD device under normal circumstances, the electrostatic prevention circuit should not interfere with or disturb driving signals. Accordingly, the electrostatic prevention circuit should have low impedance in a high voltage state and high impedance in a low voltage state.
Hereinafter, an LCD device having an electrostatic prevention circuit according to the related art will be described with reference FIG. 1 and FIG. 2.
FIG. 1 is a schematic view of a substrate for an LCD device having an electrostatic prevention circuit according to the related art.
As shown in FIG. 1, a substrate 40 (TFT array substrate) includes a plurality of gate G and data D lines crossing each other, a plurality of pixel regions P defined by the gate and data lines G and D formed in a display area 21 of the substrate 40, a plurality of pixel electrodes formed in the pixel regions P, a thin film transistor (not shown) formed in a crossing portion of the gate line G and the data line D, a common voltage line CL formed in a non-display area 22 surrounding the display area 21, and an electrostatic prevention circuit 24 electrically connected between the gate line G (or the data line D) and the common voltage line CL. That is, the common voltage line CL serves as a transmission line for transmitting common voltage to a common electrode. For that, the common voltage line CL is electrically connected with the common electrode (not shown) formed on another substrate (color filter substrate) by the medium of Ag dot. Also, liquid crystal is formed between the substrate 40 (TFT array substrate) and another substrate (color filter substrate).
During the state of a normal driving voltage, the electrostatic prevention circuit 24 serves as a sufficiently large resistance so as to have no effect on the internal driving of the thin film transistor of the substrate 40. During the state of an overvoltage generated by static electricity applied to the substrate 40, that is, to the gate lines G or data lines D, the electrostatic prevention circuit 24 functions as a discharge path. This will be described with reference to the accompanying drawings.
FIG. 2 is an expanded view of portion ‘A’ of FIG. 1. FIG. 3 is an equivalent circuit view of FIG. 2.
As shown in FIG. 2 and FIG. 3, the electrostatic prevention circuit 24 is comprised of first to third transistors T1 to T3. That is, the first transistor Ti has a gate terminal and a source terminal connected to the gate line G. The second transistor T2 has a gate terminal and a drain terminal connected to the common voltage line CL, and a source terminal connected to a drain terminal of the first transistor T1. The third transistor T3 has a gate terminal connected to a common terminal formed by connecting the drain terminal of the first transistor T1 and the source terminal of the second transistor T2, a source terminal connected to the gate line G, and a drain terminal connected to the common voltage line CL.
On driving the LCD device under the normal circumstances, the driving voltage applied to the thin film transistor through the common voltage line CL and the gate line G is lower than the driving voltage of the electrostatic prevention circuit 24 comprised of the first to third transistors (T1 to T3), so that the electrostatic prevention circuit 24 is turned off. As a result, the electrostatic prevention circuit 24 has no effect on driving the thin film transistor. However, if the static electricity of the high voltage above the driving voltage of the thin film transistor is applied to the gate line G, the static electricity is discharged to the common voltage line CL through the electrostatic prevention circuit 24. Accordingly, an equipotential generates between the gate line G and the common voltage line CL. Meanwhile, the electrostatic prevention circuit 24 connected between the data line D and the common voltage line CL has the same structure as that of the electrostatic prevention circuit 24 connected between the gate line G and the common voltage line CL. As described above, the static electricity of the data line D is discharged to the common voltage line CL according to the same method.
At this time, the thin film transistor and the first to third transistors (T1 to T3) of the electrostatic prevention circuit 24 are formed by photolithography using a plurality of masks. Recently, a 4-mask or 3-mask process using a diffraction exposure method and a lift-off method is generally used to improve yield of the thin film transistor, which substitutes for the conventional 5-mask process. As described above, in case of using the 4-mask process or 3-mask process, it is possible to decrease the usage number of the masks. However, in the 4-mask process or 3-mask process, it has the problem in deterioration of the uniformity, after ashing a photoresist, when performing an etching process for removing a metal layer and a doped semiconductor layer for channel region of the exposed thin film transistor by using the ashed photoresist as a mask.
This will be described in detail by the process (4-mask process using the diffraction exposure) of the thin film transistor.
FIG. 4A to FIG. 4G are cross sectional views of explaining the fabrication process steps of the thin film transistor using the diffraction exposure method according to the related art.
First, as shown in FIG. 4A, a metal layer is deposited on an entire surface of the substrate 40, and selectively patterned by photolithography, thereby forming a gate electrode GE, a first storage electrode ST1, and the common voltage line CL (not shown), at the same time (a first mask).
Subsequently, as shown in FIG. 4B, a gate insulating layer GI of an insulating material such as silicon oxide SiOx or silicon nitride SiNx, a semiconductor material 41 of genuine amorphous silicon, a doped semiconductor material 42 of amorphous silicon with dopants, and a metal layer 43 of chrome (Cr) or molybdenum (Mo) are sequentially deposited on the entire surface of the substrate 40 including the gate electrode GE, the first storage electrode ST1, and the common voltage line CL.
Next, as shown in FIG. 4C, a photoresist PR is coated on the entire surface of the metal layer 43, and then the coated photoresist PR is patterned by selective exposure through a diffraction mask M and development. At this time, the diffraction mask M includes an open part ml penetrating light, a closed part m2 cutting off the light, and a diffraction part m3 comprised of a slit allowing to pass a part of the light and cutting off a part of the light. The diffraction part m3 corresponds to the channel region of the thin film transistor.
When performing the exposure and development process to the photoresist PR by irradiating ultraviolet ray through the diffraction mask M, the photoresist PR corresponding to the open part m1 is removed, the photoresist PR corresponding to the closed part m2 remains as it is, and the photoresist PR corresponding to the diffraction part m3 is removed at a predetermined thickness.
Generally, the photoresist PR corresponding to the diffraction part m3 is formed to have a half of the initial thickness.
After that, the exposed metal layer 43, the doped semiconductor material of amorphous silicon with dopants 42, and the semiconductor material of intrinsic amorphous silicon 41 are removed by the etching process using the patterned photoresist PR as the mask. As a result, a first semiconductor layer 41a, a first ohmic contact layer 42a, and a source/drain metal layer 44 are formed on the gate insulating layer GI above the gate electrode GE. At this time, a second semiconductor layer 41b, a second ohmic contact layer 42b, and a second storage electrode ST2 are formed on the gate insulating layer GI above the first storage electrode ST1 (a second mask).
Then, as shown in FIG. 4D, the patterned photoresist PR is ashed by a plasma process.
The entire surface of the patterned photoresist PR is ashed at the same level by the ashing step. At this time, the photoresist PR corresponding to the diffraction part m3 is removed because the photoresist PR corresponding to the diffraction part m3 has less thickness for the other parts of the photoresist PR. Accordingly, the source/drain metal layer 44 corresponding to the diffraction part m3 is exposed.
Subsequently, the exposed source/drain metal layer 44, and the ohmic contact layer formed under the source/drain metal layer 44 are simultaneously etched by using the photoresist PR remaining after the ashing step as the mask. Thus, as shown in FIG. 4E, a channel region is formed by exposure of the first semiconductor layer 41a, and then the photoresist PR is removed. At this time, a source electrode SE overlapping one edge of the first semiconductor layer 41a, and a drain electrode DE overlapping the other edge of the first semiconductor layer 41a are formed as the source/drain metal layer 44 separates.
Referring to FIG. 4F, a passivation layer 45 of an organic insulating material is deposited on the entire surface of the substrate 40 including the source electrode SE, the drain electrode DE, the second storage electrode ST2, and the gate insulating layer GI, and then selectively patterned by photolithography, thereby forming a drain contact hole C1, and a storage contact hole C2. At this time, the drain contact hole C1 exposes some of the drain electrode DE, and the storage contact hole C2 exposes some of the second storage electrode ST2.
Then, as shown in FIG. 4G, a transparent conductive layer is deposited on the entire of the substrate 40 including the passivation layer 45, and then selectively patterned by photolithography, thereby forming a pixel electrode 46 in the pixel region P, wherein the pixel electrode 46 connects the drain electrode DE with the second storage electrode ST2 through the drain contact hole C1 and the storage contact hole C2.
Meanwhile, although not shown, the first to third transistors T1 to T3 of the electrostatic prevention circuit are manufactured by the same process as that of the thin film transistor of the display area 21. By the ashing step shown in FIG. 4C and FIG. 4E, when removing the photoresist PR formed in the channel region of the first to third transistors T1 to T3, it has a problem in that the thickness of the photoresist PR is not uniform. Accordingly, it causes deterioration in the uniformity in the etching process for removing the source/drain metal layer 44 of the channel region and the first ohmic contact layer 42a, whereby it may generate an under-etch or over-etch problems. In case of the under-etch, the channel region is not less etched, so that the first ohmic contact layer 42a of the channel region is not removed. Meanwhile, in case of the over-etch, the channel region is etched excessively, whereby the first semiconductor layer 41a positioned under the first ohmic contact layer 42a is etched. Accordingly, due to the under-etch and the over-etch problems, the thin film transistor loses the function of a switching device. As a result, even though the voltage above the driving voltage is applied to each gate line G and data line D according as static electricity generates in the inside of the LCD device, it is impossible to discharge the static electricity by using the related art electrostatic prevention circuit.